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fn9223 rev 1.00 page 1 of 20 july 28, 2008 fn9223 rev 1.00 july 28, 2008 ISL8101 two-phase multiphase buck pwm controller with integrated mosfet drivers datasheet the ISL8101 two-phase pwm control ic provides a precision voltage regulation syst em for advanced loads up to 60a to 80a. multiphase power conversion is a marked departure from single phase co nverter configurations employed to satisfy the inc reasing current demands of modern microprocessors and other electronic circuits. by distributing the power and load current, implementation of multiphase converters utiliz e smaller and lower cost transistors with fewer input and output capacitors. these reductions accrue from the hi gher effective conversion frequency with higher frequency ripple current due to the phase interleaving process of this topology. outstanding features of this con troller ic include programmable vid codes compatible with intel vrm9, vrm10, as well as amds hammer microprocesso rs, along with a system regulation accuracy of ? 1%. the ISL8101, though, does not intrinsically allow for load-line regulation (no droop). important features of this controller ic include a set of sophisticated overvoltage a nd overcurrent protection. overvoltage results in the c onverter turning the lower mosfets on to clamp the rising output voltage and protect the microprocessor. like ot her intersil multiphase controllers, the ISL8101 use s cost and space-saving r ds(on) sensing for channel current balance and overcurrent protection. cha nnel current balancing is automatic and accurat e with the integrated current-balance control system. overcurrent protection can be tailored to any application with no need for addi tional parts. these features provide intelligent protec tion for modern power systems. features ? integrated two-phas e power conversion ? 5v to 12v input voltage conversion ? precision channel current sharing - loss-less current sampling - uses r ds(on) ? precision output voltage regulation - ? 1% system accuracy over-t emperature ( commercial) ? microprocessor voltag e identification inputs - up to a 6-bit dac - selectable between intel s vrm9, vrm10, or amds hammer dac codes ? fast transient recovery time ? overcurrent protection ? pre-biased output s tart-up operation ? sources and sinks output current - bus termination applications ? improved, multi-tiered overvoltage protection ? qfn package: - compliant to jedec pub95 mo-220 qfn - quad flat no leads - package outline - near chip scale package f ootprint, which improves pcb efficiency and has athinner profile ? pb-free (rohs compliant) pinout ISL8101 (24 ld qfn) top view ordering information part number (note) part marking temp. (c) package pkg. dwg. # ISL8101crz* (note) 81 01crz 0 to +70 24 ld 4x4 qfn (pb-free) l24.4x4b ISL8101irz* (note) 81 01irz -40 to +85 24 ld 4x4 qfn (pb-free) l24.4x4b ISL8101eval1 evaluation platform *add -t suffix for tape and reel. please refer to tb347 for details on reel specifications. note: these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb -free peak reflow temperatures that meet or exceed the pb-free requirement s of ipc/jedec j std-020. vid1 vrm10 vid0 dacsel/vid5 comp fb isen vcc ofs ssend boot2 ugate2 vid2 vid3 vid4 enll boot1 ugate1 lgate2 pgnd phase1 lgate1 pvcc phase2 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 25 gnd o b s o l e t e p r o d u c t n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
fn9223 rev 1.00 page 2 of 20 july 28, 2008 ISL8101 block diagram soft-start boot1 comp vid2 vid3 vid1 fb power-on reset (por) ttl d/a converter (vid dac) and fault logic gnd vid4 vid0 ? ? control logic gate control gate control oscillator current correction + - oc ea pwm1 pwm2 ovp isen 2 ? 200mv pvcc disabled ovp while 1.65v/1.95v vcc dacsel/vid5 ofs enll ssend phase1 lgate1 ugate1 pgnd phase2 lgate2 ugate2 boot2 + - vrm10 + - offset source
ISL8101 fn9223 rev 1.00 page 3 of 20 july 28, 2008 simplified power system diagram typical application channel1 +5v in v out q 1 q 2 ISL8101 channel2 q 3 q 4 dac 5-6 vid ISL8101 +12v in q 1 q 2 q 3 q 4 vid4 vid3 vid2 vid1 vid0 comp fb gnd v cc boot1 boot2 ugate1 ugate2 isen lgate1 lgate2 l in l out1 c hfin1 c bin1 c hfin2 c bin2 c boot1 c boot2 l out2 c hfout c bout r isen r 2 r 1 c 1 c 2 c f1 phase1 phase2 v out pgnd p vcc c f2 +5v in dacsel/vid12 vrm10 ssend enll r ofs ofs r ofs
ISL8101 fn9223 rev 1.00 page 4 of 20 july 28, 2008 absolute maximum ratings supply voltage, v cc , p vcc . . . . . . . . . . . . . . . . . . . -0.3v to +6.25v absolute boot voltage, v boot . . . . . . p gnd - 0.3v to p gnd + 27v phase voltage, v phase . . . . . . . . . . v boot - 7v to v boot + 0.3v upper gate voltage, v ugate . . . . v phase - 0.3v to v boot + 0.3v lower gate voltage, v lgate . . . . . . . . . p gnd - 0.3v to v cc + 0.3v input, output, or i/o voltage . . . . . . . . . . gnd - 0.3v to v cc + 0.3v recommended operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v ? 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c thermal information thermal resistance ? ja (c/w) ? jc (c/w) qfn package (notes 1, 2). . . . . . . . . . 45 7.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +1 50c pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. electrical specifications test conditions: v cc = 5v, t j = 0c to +85c, unless otherwise specified. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits established by characterization and are not production tested. parameter test conditions min typ max units bias supply and internal oscillator input bias supply current i vcc ; enll = high - 4 6 ma vcc por (power-on reset) threshold vcc rising 4.2 4.4 4.6 v vcc falling 3.7 3.9 4.1 v pvcc por (power-on reset) threshold pvcc rising - 4.3 - v pvcc falling - 3.3 - v switching frequency (per channel) t j = +25c to +85c 189 222 255 khz t j = -40c 166 205 241 khz oscillator ramp amplitude (note 3) v p-p -1.33-v maximum duty cycle -67-% control thresholds enll rising threshold -0.645- v enll falling threshold -0.567-mv reference and dac system accuracy -1 - 1 % t j = -40c to +85c -1.5 - 1.5 % dac input low voltage --0.4v dac input high voltage 0.8 - - v dac input pull-up current vidx = 0v - 45 - a error amplifier dc gain (note 3) r l = 10k to ground - 96 - db gain-bandwidth product (note 3) c l = 100pf, r l = 10k to ground - 20 - mhz slew rate (note 3) c l = 100pf, load = ? 400a - 8 - v/s maximum output voltage load = 1ma 3.90 4.20 - v minimum output voltage load = -1ma - 0.80 0.90 v ISL8101
ISL8101 fn9223 rev 1.00 page 5 of 20 july 28, 2008 timing diagram functional pin description vcc (pin 8) bias supply for the ics small-si gnal circuitry. connect this pin to a 5v supply and locally decouple using a quality 0.1f ceramic capacitor. this pin is monitored for power-on reset (por) purpose. pvcc (pin 16) power supply pin for the mosfet drives. connect this pin to a 5v supply and locally dec ouple using a quality 1f ceramic capacitor. this pin is monitored for por purpose. gnd and pgnd (pins 25 and 14) connect these pins to the circu it ground using the shortest possible paths. all internal small-signal circuitry is overcurrent protection overcurrent trip level 72 95 115 a protection overvoltage threshold while ic d isabled vrm9.0 configuration 1.90 1.95 2.00 v hammer and vrm10.0 configurations 1.60 1.65 1.70 v overvoltage threshold fb rising - vid +200mv -v overvoltage hysteresis - 100 - mv switching time ugate rise time (note3) t rugate; v vcc = 5v, 3nf load - 8 - ns lgate rise time (note3) t rlgate; v vcc = 5v, 3nf load - 8 - ns ugate fall time (note 3) t fugate; v vcc = 5v, 3nf load - 8 - ns lgate fall time (note 3) t flgate; v vcc = 5v, 3nf load - 4 - ns ugate turn-on non-overlap (note 3) t pdhugate ; v vcc = 5v, 3nf load - 8 - ns lgate turn-on non-overlap (note 3) t pdhlgate ; v vcc = 5v, 3nf load - 8 - ns output upper drive source resistance 100ma source current - 1.0 2.5 ? upper drive sink resistance 100ma sink current - 1.0 2.5 ? lower drive source resistance 100ma source current - 1.0 2.5 ? lower drive sink resistance 100ma sink current - 0.4 1.0 ? note: 3. limits should be considered ty pical and are not production te sted. electrical specifications test conditions: v cc = 5v, t j = 0c to +85c, unless otherwise specified. parameters with mi n and/or max limits are 100% tested at +25c, unless otherwise specified. te mperature limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate
ISL8101 fn9223 rev 1.00 page 6 of 20 july 28, 2008 referenced to the gnd pin. lga te drive is referenced to the pgnd pin. vid0-4 (pins 2, 1, 24-22) voltage identification inputs fr om microprocessor. these pins respond to ttl logic threshol ds. the ISL8101 decodes the vid inputs to establish the output voltage; see vid tables beginning on page 9 for cor respondence between dac codes and output voltage settings. these pins are internally pulled high, to approximately 1.2v, by 40a (typically) internal current sources; the internal pull-up current decrease to 0 as the vid voltage approaches the in ternal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ics bias voltage. dacsel/vid5 (pin 3) if vrm10 pin is grounded, dacsel/vid5 represents the 6th voltage identification input from the vrm10-compliant microprocessor, otherwise known as vid5. if vrm10 pin is open or pulled high, dacsel/vid5 selects the compliance standard for the internal dac: pulled to ground it encodes the dac with amd hammer vid codes , while left open or pulled high, it encodes the dac with intel vrm9.0 codes. vrm10 (pin 4) this pin selects vrm10.0 dac compliance when grounded. left open, it allows selection of either vrm9. 0 or hammer dac compliance via dacsel pin. enll (pin 21) this pin is a precision-threshold (approximately 0.6v) enable pin. held low, this pin disables controller operation. pulled high, the pin enables the controller for operation. fb and comp (pins 6, 5) the internal error amplifier s inverting i nput and output respectively. these pins are connected to the external network used to compensate the regulators feedback loop. an internal current source inj ects the offset (ofs) current sampled into the fb pin. pulling comp to ground through an impedance lower than 15 ? disables the controller (same effect as enll pulled low). isen (pin 7) this pin is used to close the current-balance loop and set the overcurrent protection threshold. a resistor connected between this pin and v cc has a voltage drop forced across it equal to that sampled acr oss the lowe r mosfets r ds(on) during approximately the middle of its conduction interval. the resulting current through this resistor is used for channel current balancing and overcurrent protection. the voltage across the r isen resistor is time mult iplexed between the two channels. to select the proper r isen resistor, use equation 1. where: r ds(on)max = lower mosfets highest drain-source on resistance ( ? ; include temperature effects) i out = channel maximum output current (a) see channel balance current loop on page 7 for more information. ugate1, 2 (pins 19, 12) connect these pins to the upper mosfets gates. these pins are used to control t he upper mosfets and are monitored for shoot-through prevention purposes. maximum individual channel duty cycle is limited to 66%. boot1, 2 (pins 20, 11) these pins provide the bias voltage for the upper mosfets drives. connect these pins to a ppropriately-chosen external bootstrap capacitors. internal bootstrap diodes connected to the pvcc pins provide the nec essary bootstrap charge. phase1, 2 (pins 18, 13) connect these pins to the sou rces of the upper mosfets. these pins are the return path for t he upper mosfets drives. lgate1, 2 (pins 17, 15) these pins are used to control the lower mosfets and are monitored for shoot-through prevention purposes. connect these pins to the lo wer mosfets gates. ofs (pin 9) this pin is used to create an adj ustable output voltage offset. for no offset, leave this pin open. for negative offset, connec t a r ofs resistor from this pin to v cc and size it according to equation 2. where: v offset = desired output volta ge offset magnitude (mv) for positive output voltage offset, connect a r ofs resistor from this pin to gnd, sizing it according to equation 3. for more information, refer to output voltage setting on page 9 . ssend (pin 10) this pin is an end of soft-st art (ss) indicator; open drain output device stays on during soft-start, and goes open when soft-start ends. r isen r ds on ?? max i out ? 95 ? a ------------------------------------------------------ - = (eq. 1) r ? ofs r 1 1500 v offset -------------------------- ? = (eq. 2) r ofs r 1 500 v offset -------------------------- ? = (eq. 3)
ISL8101 fn9223 rev 1.00 page 7 of 20 july 28, 2008 operation the ISL8101 employs simple voltage-mode control. figure 1 shows a simplified diagram of the voltage regulation and current balance loops. voltage feedback is used to precisely regulate the output voltage, w hile current feedback tightly controls the individu al channel currents, i l1 and i l2 , and trips the oc protecti on, if so necessary. voltage loop feedback from the output voltage is applied via resistor r 1 to the inverting input of the er ror amplifier. this signal can drive the error amplifier outpu t either high or low, depending upon the output voltage. low output voltage makes the amplifier output move towards a higher output voltage level. amplifier output voltage is appl ied to the positive inputs of the pwm circuit comparators via the channel current correction summing networ ks. out-of-phase sawtooth signals are applied to the two pwm comparators inverting inputs. increasing error amplifier voltage results in increased comparator output duty cycle. this in creased duty cycle signal is passed through the output drivers with no phase reversal to drive the external upper mosfets. increased duty cycle or on time for t he upper mosfet transistors results in increased output voltage to compensate for the low output voltage sensed. channel balance current loop the current balance control loop works in a similar fashion to the voltage control loop, but wit h current control information applied individually to each channels pwm circuit. the information used for this con trol is the vo ltage that is developed across the r ds(on) of each lower mosfet, while they are conducting. a single resistor converts and scales the voltage across the mosfets to a current that is applied to the current sensing circu it within the ISL8101. output from these sensing circuits is applied to the current averaging circuit. each pwm channel receives the difference current signal fro m the summing circuit that compares the average sensed current to the individual channel current. when a power channels current is greater than the average current, the signal applied via the summing correction circuit to the com parator, reduces the output pulse width of the comparator to compensate for the detected above average current in that channel. multiphase power conversion multiphase power conversion provides a cost-effective power solution when load curr ents are no longer easily supported by single- phase converters. although its greater complexity presents additional technical challenges, the multiphase approach offers cost-saving advantages with improved response time, super ior ripple cancellation, and thermal distribution. figure 1. simplified block diag ram of the ISL8101 voltage and cu rrent feedback average current sense ? ? ? dac and reference pwm circuit pwm circuit half-bridge drive half-bridge drive ? oscillator comp fb l 1 l 2 c out v out v in v in r isen ugate1 ugate2 lgate1 lgate2 phase1 phase2 isen current sense v cc r 1 r 2 c 2 error amp ISL8101
ISL8101 fn9223 rev 1.00 page 8 of 20 july 28, 2008 interleaving the switching of each channel in a ISL8101-based converter is timed to be symmetrically out of phase with the other channel. as a result, the t wo-phase converter has a combined ripple frequency twice the frequency of one of its phases. in addition, the peak -to-peak amplitude of the combined inductor currents is proportionately reduced. increased ripple frequency and lower ripple amplitude generally translate to lowe r per-channel inductance and lower total output capacitance for a given set of performance specifications. figure 2 illustrates the additi ve effect on output ripple frequency. the two channel currents (i l1 and i l2 ), combine to form the ac ripple current and the dc load current. the ripple component has two times the ripple frequency of each individual channel current. to understand the reduction of ripple current amplitude in the multiphase circuit, exami ne equation 4 representing an individual channels peak-to-peak inductor current. v in and v out are the input and output voltages, respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitor s conduct the ripp le component of the inductor current. in the case o f multiphase converters, the capacitor current is the sum o f the ripple currents from each of the individual channels (see equation 5). peak-to-peak ripple current, i p-p , decreases by an amount proportional to the number of channels. output-voltage ripple is a function of capac itance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors (should output ripple be an important design parameter). another benefit of interleaving is the reduction of input rippl e current. input capacitance is determined in a large part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in f igure 3 illustrates input currents from a two-phase con verter combining to reduce the total input ripple current. figure 12, part of the sectio n entitled input capacitor selection on page 19, can b e used to determine the input-capacitor rms current based on load current and duty cycle. the figure is p rovided as an aid in determining the optimal input capacitor solution. pwm operation one switching cycle fo r the ISL8101 is defined as the time between consecutive pwm pulse terminations (turn-off of the upper mosfet on a chann el). each cycle begins when a switching clock signal co mmands the upper mosfet to go off. the other channels upper mosfet conduction is terminated 1/2 of a cycle later. once a channels upper mosfe t is turned off, the lower mosfet remains on for a mini mum of 1/3 cycle. this forced off time is required to assure an accurate current sample. following the 1/3-cycle forced off time, the controller enables the upper mosfet output. once enabled, the upper mosfet output transitions hi gh when the sawtooth signal crosses the adjusted error-a mplifier output signal, as illustrated in the ISL8101s blo ck diagram. just prior to the upper drive turning the mosf et on, the lower mosfet figure 2. pwm and inductor-current waveforms for 2-phase converter pwm2 pwm1 i l2 i l1 i l1 + i l2 i lp-p ? v in v out C ?? v out ? lf s v ? in ? --------------------------------------------------------- - = (eq. 4) i p-p v in nv out ? C ?? v out ? lf s v ? in ? --------------------------------------------------------------- ---- - = (eq. 5) figure 3. input capacitor current and individual channel currents in a 2-phase converter q1 d-s current q3 d-s current c in current
ISL8101 fn9223 rev 1.00 page 9 of 20 july 28, 2008 drive turns the freewheelin g element off. the upper mosfet is kept on un til the clock signals the beginning of the next switching cycle and the pwm pulse is terminated. current sensing ISL8101 senses current by samp ling the voltage across the lower mosfet during its co nduction interval. mosfet r ds(on) sensing is a no-added-cost method to sense current for channel current balance and overcurrent protection. the phase pins are used as inputs for each channel. internal circuitry sampl es the lower mosfets r ds(on) voltage, once each cycle, during their conduction periods and time multiplexes the sampled voltages across the isen resistor. the current that is thus developed through the isen resistor is duplicated and used for channel current balancing and overcurrent detection. channel-current balance another benefit of multiphase operation is the thermal advantage gained by distributi ng the dissipated heat over multiple devices and greater area. by doing this, the designer avoids the complexity of driving multiple parallel mosfets and the expense of using expensive heat sinks and exotic magnetic materials. in order to fully realize the ther mal advantage, it is importan t that each channel in a multiphase converter be controlled to deliver about the same curren t at any load level. intersil multiphase controllers ensure current balance by comparing each channels current to the average current delivered by all channels and making approp riate adjustments to each channels pulse width based on the error. the error signal modifies the pulse width to corr ect any unbalance and force the error toward zero. overcurrent protection the individual channel currents, as sensed via the phase pins and scaled via the isen resistor, are continuously monitored and compared with an internal 95a reference current. if both channels curr ents exceed, at any time, the reference current, t he overcurrent comparator triggers an overcurrent event. similarly, an oc event is also triggered if either channels current exceed s the 95a reference for 7 consecutive switching cycles. as a result of an oc event, out put drives on both channels turn off both upper and lower mosfets . the system then waits in this state for a peri od of 4096 switching clock cycles . the wait period is followed by a soft-start attempt . if the soft-start attempt i s successful, operat ion continues as normal. should the soft-start attempt fail, the ISL8101 repeats the 2048-cycle wait per iod and follows with another soft-start attempt. this hicc up mode of opera tion continues indefinitely (as depicted in f igure 4) for as long as the controller is enabled or until the overcu rrent condition is removed. output voltage setting the ISL8101 uses a digital to analog converter (dac) to generate a reference voltage based on the logic signals at the vid pins. the dac decodes the 5 or 6-bit logic signals into one of the discrete voltages shown in tables 1, 2 and 3. each vid pin is pulled up to an i nternal 1.2v voltage by weak current sources (about 45a cur rent, decreasing to 0 as the voltage at the vid pins varies from 0 to the internal 1.2v pull - up voltage). external pull-up r esistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5v. . the ISL8101 accommodates three different dac ranges: intel vrm9.0, amd hammer, or intel vrm10.0. see functional pin description on page 5 for proper connections for desired dac range compatibility. table 1. amd hammer voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111100.800 111010.825 111000.850 110110.875 110100.900 110010.925 110000.950 101110.975 101101.000 101011.025 101001.050 100111.075 output current figure 4. overcurrent behavior in hiccup mode output voltage
ISL8101 fn9223 rev 1.00 page 10 of 20 july 28, 2008 100101.100 100011.125 100001.150 011111.175 011101.200 011011.225 011001.250 010111.275 010101.300 010011.325 010001.350 001111.375 001101.400 001011.425 001001.450 000111.475 000101.500 000011.525 000001.550 table 2. vrm9 voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111101.100 111011.125 111001.150 110111.175 110101.200 110011.225 110001.250 101111.275 101101.300 101011.325 101001.350 100111.375 100101.400 100011.425 100001.450 table 1. amd hammer voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vdac 011111.475 011101.500 011011.525 011001.550 010111.575 010101.600 010011.625 010001.650 001111.675 001101.700 001011.725 001001.750 000111.775 000101.800 000011.825 000001.850 table 3. vrm10 voltage identification codes vid4 vid3 vid2 vid1 vid0 vid5 vdac 111111off 111110off 0 1 0 1 0 0 0.8375 0 1 0 0\ 1 1 0.8500 0 1 0 0 1 0 0.8625 0 1 0 0 0 1 0.8750 0 1 0 0 0 0 0.8875 0 0 1 1 1 1 0.9000 0 0 1 1 1 0 0.9125 0 0 1 1 0 1 0.9250 0 0 1 1 0 0 0.9375 0 0 1 0 1 1 0.9500 0 0 1 0 1 0 0.9625 0 0 1 0 0 1 0.9750 0 0 1 0 0 0 0.9875 0 0 0 1 1 1 1.0000 0 0 0 1 1 0 1.0125 0 0 0 1 0 1 1.0250 0 0 0 1 0 0 1.0375 0 0 0 0 1 1 1.0500 0 0 0 0 1 0 1.0625 0 0 0 0 0 1 1.0750 table 2. vrm9 voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vdac
ISL8101 fn9223 rev 1.00 page 11 of 20 july 28, 2008 dynamic vid (vid-on-the-fly) the ISL8101 is capable of e xecuting on-the-fly output voltage changes. the way the ISL8101 reacts to a change in the vid code is dependent on the vid confi guration. in vrm9 or amd hammer settings , the ISL8101 checks for a change in the vid code four tim es each switching cycle. the vid code is the bit pattern present at pins vid4-vid0. if a new code is established and i t stays the same for 12 switching cycles, the ISL8101 begins changing the reference by making one step change every four switching cycles until it reaches the new vid code . figure 5 depicts such a transition, from 1.5v to 1.7v in vrm10 setting, the ISL8101 checks for a change in the vid code six times each switching cycle. if a new code is established and it stays the same for 3 consecutive readings, the ISL8101 recognizes the change and increments the reference. specific to vrm10, t he processor controls the vid transitions and is responsib le for incrementing or decrementing one vid step a t a time. in vrm10 setting, the ISL8101 will immediately change the reference to the new requested value as soon as the r equest is validated; in cases where the reference step is too large, the sudden change can trigger overcurrent or overvoltage events. in non-vrm10 settings, due to the way the ISL8101 recognizes vid code changes , up to one full switching period may pass before a vid change registers. thus, the total time required for a vid change, t dvid , is dependent on the switching frequency (f s ), the size of the change ( ? v id ), and the time required to reg ister the vid change. the approximate time required for a ISL8101-based converter in vrm9 configuration running at typical f s (222khz) to perform a 1.5v-to- 1.7v reference vol tage change is about 196s, as calculated using equation 6. (this example is also illustrated in figure 5). 0 0 0 0 0 0 1.0875 1 1 1 1 0 1 1.1000 1111001.1125 1 1 1 0 1 1 1.1250 1 1 1 0 1 0 1.1375 1 1 1 0 0 1 1.1500 1 1 1 0 0 0 1.1625 1 1 0 1 1 1 1.1750 1 1 0 1 1 0 1.1875 1 1 0 1 0 1 1.2000 1 1 0 1 0 0 1.2125 1 1 0 0 1 1 1.2250 1 1 0 0 1 0 1.2375 1 1 0 0 0 1 1.2500 1 1 0 0 0 0 1.2625 1 0 1 1 1 1 1.2750 1 0 1 1 1 0 1.2875 1011011.300 1 0 1 1 0 0 1.3125 1 0 1 0 1 1 1.3250 1 0 1 0 1 0 1.3375 1 0 1 0 0 1 1.3500 1 0 1 0 0 0 1.3625 1 0 0 1 1 1 1.3750 1 0 0 1 1 0 1.3875 1 0 0 1 0 1 1.4000 1 0 0 1 0 0 1.4125 1 0 0 0 1 1 1.4250 1 0 0 0 1 0 1.4375 1 0 0 0 0 1 1.4500 1 0 0 0 0 0 1.4625 0 1 1 1 1 1 1.4750 0 1 1 1 1 0 1.4875 0 1 1 1 0 1 1.5000 0 1 1 1 0 0 1.5125 0 1 1 0 1 1 1.5250 0 1 1 0 1 0 1.5375 0 1 1 0 0 1 1.5500 0 1 1 0 0 0 1.5625 0 1 0 1 1 1 1.5750 0 1 0 1 1 0 1.5875 0 1 0 1 0 1 1.6000 table 3. vrm10 voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vdac figure 5. typical dynamic-vid operation, vrm9 dac setting 1.5v v vid 01110 00110 1.5v vid change occurs here v ref (100mv/div) v out (100mv/div) t dvid 1 f s ---- - 4v ? vid 0.025 -------------------- - 13 + ?? ?? ?? ? (eq. 6)
ISL8101 fn9223 rev 1.00 page 12 of 20 july 28, 2008 overvoltage protection the ISL8101 benefits from a multi-tiered approach to overvoltage protection. a pre-por mechanism is at wor k while the chip does not have sufficient bias voltage to initiate an active response to an ov situation. thus, while vcc is below its por level, the lower drives are three-stated and internal 5k ? (typically) resistors are connected from phase to their respective lgate pins. as a result, out put voltage, duplicated at the phase nodes via the output in ductors, is effectively clamped at the lower mosfet s threshold level. this approach ensures no catastr ophic output voltage can be developed at the output of an is l8101-based regulator (for most typical applications). the pre-por mechanism is removed once the bias is above the por level, and a fixed-t hreshold ovp goes into effect. based on the specific chip conf iguration, the ovp goes into effect once the voltage sensed at the fb pin exceeds about 1.65v (hammer/vr10) or 1.95v (vr9 configuration). should the output voltage exceed thes e thresholds, the lower mosfets are turned on. during soft-start, the ovp threshold changes to the higher of the fixed threshold (1.65v/1.9 5v) or the dac setting plus 200mv. at the end of the soft-start, the ovp threshold changes to the dac setting plus 200mv. in any of the described post-po r functionality, ovp results in the turn-on of the lower m osfets. once turned on, the lower mosfets are only turned off when the output voltage drops below the ov comparator s hysteretic threshold. the ovp process repeats if the v oltage rises back above the designated threshold. the occurrence of an ovp event does not latch the controller ; should the phenomenon be transitory, the controller re sumes normal operation following such an event. on/off control the internal power-on reset circuit (por) prevents the ISL8101 from starting before the bias voltage at vcc and pvcc reach the rising por t hresholds, as defined in electrical specifications on page 4. the por levels are sufficiently high to guarantee that all parts of the ISL8101 can perform their functions prope rly once bias is applied to the part. while bias is below the rising por thresholds, the controlled mosfets are kept in an off state. a secondary disablement feat ure is available via the threshold-sensitive enable input (enll). this optional feature prevents the ISL8101 f rom operating until a certain other voltage rail is availabl e and above some selectable threshold. for example, when down-converting off a 12v input, it may be desirable the ISL8101-based converter does not start up until the power i nput is sufficiently high. the schematic in figure 6 demonstrates coo rdination of the ISL8101 with such a rail; t he resistor components are chosen to enable the ISL8101 as the 12v input exceeds approximately 9.75v . additionally, an o pen-drain or open- collector device can be used to wire-and a second (or multiple) control signa l, as shown in figur e 6. to defeat the threshold-sensitive enable, connect enll to vcc directly or via a pull-up resistor. the 11111 vid code is reserved as a signal to the controller that no load is pres ent. the controller is disabled while receiving this vid code and will subsequently start up upon receiving any other code. in summary, for the ISL8101 to operate, th e following conditions need be met: v cc and p vcc must be greater than their respective por thr esholds, the voltage at enll must be greater than 0.61v, and vid has to be different than 11111. once all these condit ions are met, the controller immediately initiates a soft-start sequence. soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. following a delay o f 16 phase clock cycles (about 70s) between enabling the chip and the start of the ramp, the output voltage pr ogresses at a fixed r ate of 12.5mv per 16 phase clock cycles. thus, the soft-start period (not including the 70s wait) up to a given voltage, v dac , can be approxima ted by equation 7. where v dac is the dac-set vid voltage, and f s is the switching frequency (typically 222khz). the ISL8101 also has the abi lity to start-up into a pre-charged output, without causing any unnecessary disturbance. the fb pin is mon itored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping re ference exceeds the fb pin figure 6. start-up coordination using threshold- sensitive enable (enll) pin - + 0.61v external circuit ISL8101 enll +12v v cc +5v por circuit 15k ? 1k ? enable comparator off on t ss v dac 1280 ? f s --------------------------------- = (eq. 7)
ISL8101 fn9223 rev 1.00 page 13 of 20 july 28, 2008 potential, the output drives are enabled, allowing the output to ramp from the pre-charged leve l to the final level dictated by the dac setting. should t he output be pre- charged to a level exceeding the dac sett ing, the output drives are enabled at the end of the soft -start period, leading to an abrupt correction in the output voltage down to the dac-set level. frequency compensation the ISL8101 multiphase conv erter behaves in a similar manner to a voltage-mode controller. this section highlights the design consideration for a voltage-mode controller requirin g external compensation. to address a broad range of applications, a type-3 feedback network is recommended. figure 8 highlights the volt age-mode control loop for a synchronous-rectified buck conver ter, applicable, with a small number of adjustments, to the multiphase ISL8101 circuit. the output voltage (v out ) is regulated to the reference voltage, vref, level. the error amplifier output (comp pin voltage) is compared with the oscillator (o sc) modified saw-tooth wave to provide a pulse-width modulate d wave with an amplitude of v in at the phase node. the pwm wave is smoothed by the output filter (l and c). the output filter capacit or banks equivalent series resistance is represent ed by the series resistor e. the modulator transfe r function is the small-signal transfer function of v out /v comp . this function is dominated by a dc gain, given by d max v in /v osc , and shaped by the output filter, with a double pole break frequency at f lc and a zero at f ce . for the purpose of this analysis, l and d represent the individual channel inductance and its dcr divided by 2 (equivalent parallel value of the two output inductors), while c and e represents the total output capacitance and its equivalent series resistance (see equation 8). the compensation net work consists of the error amplifier (internal to the isl81 01) and the external r 1 -r 3 , c 1 -c 3 components. the goal of the co mpensation network is to provide a closed loop transfer function with high 0db crossing frequency (f 0 ; typically 0.1 to 0.3 of f sw ) and adequate phase margin (better than 45). phas e margin is the difference between the clos ed loop phase at f 0db and 180 . equations 9,10, 11, and 12 rel ate the compensatio n networks poles, zeros and gain to the components (r 1 , r 2 , r 3 , c 1 , c 2 , and c 3 ) (see figure 8). use the following guidelines for locating the poles and zeros of the compensation network: 1. select a value for r 1 (1k ? to 5k ? , typically). calculate value for r 2 for desired converter bandwidth (f 0 ). 2. calculate c 1 such that f z1 is placed at a fraction of the f lc , at 0.1 to 0.75 of f lc (to adjust, change the 0.5 factor to desired number). the higher the quality factor of the output filter and/or the h igher the ratio f ce /f lc , the lower the f z1 frequency (to maximize phase boost). figure 7. soft-start waveforms for ISL8101-based multiphase converter enll (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level f lc 1 2 ? lc ? ? --------------------------- = f ce 1 2 ? ce ?? ----------------------- - = (eq. 8) figure 8. voltage-mode buck converter compensation design - + e/a v ref comp c 1 r 2 r 1 fb c 2 r 3 c 3 l c v in pwm circuit half-bridge drive oscillator e external circuit ISL8101 v out v osc d ugate phase lgate r2 v osc r 1 f 0 ?? d max v in f lc ?? --------------------------------------------- = (eq. 9) c 1 1 2 ? r 2 0.5 f lc ?? ? ---------------------------------------------- - = (eq. 10)
ISL8101 fn9223 rev 1.00 page 14 of 20 july 28, 2008 3. calculate c 2 such that f p1 is placed at f ce . 4. calculate r 3 (see equation 12) such that f z2 is placed at f lc . calculate c 3 such that f p2 is placed below f sw (typically, 0.5 to 1.0 times f sw ). f sw represents the per-channel switching frequency. change the numerical factor to reflect desired plac ement of this pole. placement of f p2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the hf ripple component at the comp pin and minimizing resultant duty cycle jitter. it is recommended a mathemat ical model is used to plot the loop response. check the lo op gain against the error amplifiers open-loop gain. verify phase margin results and adjust as necessary. equati ons 13 and 14 describe the frequency response of the modulator (g mod ), feedback compensation (g fb ) and closed-l oop response (g cl ): compensation break frequency equations figure 9 shows an asymptotic plot of the dc/dc converters gain vs. frequency. the actual mo dulator gain has a high gain peak dependent on the quality fact or (q) of the output filter, which is not shown. using the abov e guidelines should yield a compensation gain similar to the curve plotted. the open loop error amplifier gain bounds the compensation gain. check the compensation gain at f p2 against the capabilit ies of the error amplifier. the closed loop gain, g cl , is constructed on the log-log graph of figure 9 by a dding the modulator gain, g mod (in db), to the feedback compensation gain, g fb (in db). this is equivalent to multiplying the modulator transfer function and t he compensation transfer function and then plotting the resulting gain. a stable control loop has a gain crossing with close to a -20db/decade slope and a phas e margin greater than 45. include worst case component v ariations when determining phase margin. the mathemati cal model presented makes a number of approxim ations and is generally not accurate at frequencies approaching or e xceeding half t he switching frequency. when designing c ompensation networks, select target crossover frequencies in the range of 10% to 30% of the per-channel switching frequency, f sw . general application design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a multiphase power converter. it is assumed th at the reader is familiar with many of the basic skills and te chniques referenced below. in addition to this guide, intersil provides complete reference designs that include schemati cs, bills of materials, and example board layouts for all common microprocessor applications. mosfets given the fixed switching frequency of the ISL8101 and the integrated output dri ves, the selection o f mosfets revolves closely around the current each mosfet is required to conduct, the capability of the devices to dissipate heat, as we ll as the characteristics of ava ilable heat sin king. since the ISL8101 drives the mosfets with 5v, the selection of appropriate mosfets should be done by comparing and evaluating their characte ristics at this specific v gs bias voltage. lower mosfet power calculation since virtually all of the heat l oss in the lower mosfet is conduction loss (due to cu rrent conducted through the channel resistance, r ds(on) ), a quick approximation for heat c 2 c 1 2 ? r 2 c 1 f ce 1 C ??? ------------------------------------------------------- - = (eq. 11) r 3 r 1 f sw f lc ------------ 1 C --------------------- - = c 3 1 2 ? r 3 0.7 f sw ?? ? ------------------------------------------------ - = (eq. 12) g mod f ?? d max v in ? v osc ----------------------------- - 1sf ?? ec ?? + 1sf ?? ed + ?? c ?? s 2 f ?? lc ?? ++ --------------------------------------------------------------- ------------------------- ? = g fb f ?? 1sf ?? r 2 c 1 ?? + sf ?? r 1 c 1 c 2 + ?? ?? ---------------------------------------------------- ? = 1sf ?? r 1 r 3 + ?? c 3 ?? + 1sf ?? r 3 c 3 ?? + ?? 1sf ?? r 2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? ?? ?? ?? + ?? ?? ?? ? --------------------------------------------------------------- ---------------------------------------------------------- ? g cl f ?? g mod f ?? g fb f ?? ? = where s f ?? ? 2 ? fj ?? = (eq. 13) f z1 1 2 ? r 2 c 1 ?? ------------------------------ - = f z2 1 2 ? r 1 r 3 + ?? c 3 ?? ------------------------------------------------- = f p1 1 2 ? r2 c 1 c 2 ? c 1 c 2 + -------------------- - ?? --------------------------------------------- = f p2 1 2 ? r 3 c 3 ?? ------------------------------ - = (eq. 14) 0 f p1 f z2 open loop e/a gain f z1 f p2 f lc f ce compensation gain gain frequency modulator gain figure 9. asymptotic bode plot of converter gain closed loop gain 20 r 2 r 2 ------- ?? ?? ?? log log log f 0 g mod g fb g cl 20 d max v ? in v osc --------------------------------- log
ISL8101 fn9223 rev 1.00 page 15 of 20 july 28, 2008 dissipated in the lower mo sfet can be found in equation 15. where: i m is the maximum continuous output current, i l,p-p is the peak-to-peak inductor cu rrent, and d is the duty cycle (approximately v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additi onal loss accrued during the dead time when inductor curre nt is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f s ; and the length o f dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval, respectively. equation 16 assumes the current through the lower mosfet is always posit ive; if so, the total power dissipated in each lower mosfet is approximated by the summation of p lmos1 and p lmos2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper mosfet losses are switchin g losses, due to currents conducted through the device while the input voltage is present as v ds . upper mosfet losses can be divided into separate components, separating the upper mosfet switching losses, the lower mosfet body diode reverse recovery charge loss, and the upper mosfet r ds(on) conduction loss. in most typical circuits, when the upper mosfet turns off, it continues to conduct the inducto r current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting (via its body diode or enhancement channel), the cu rrent in the upper mosfet falls to zero. in the following equation, the required time for this commutation is t 1 and the associated power loss is p umos,1 . similarly, the upper mosfet b egins conducting as soon as it begins turning on. assuming t he inductor current is in the positive domain, the upper mosfet sees approximately the input voltage applied across its drain and source terminals, while it turns on an d starts conducting t he inductor current. this transition o ccurs over a time t 2 , and the approximate the power loss is p umos,2 . a third component involve s the lower mosfets reverse-recovery charge, q rr . since the lower mosfets body diode conducts the full i nductor current before it has fully switched to the upper mosfet, the upper mosfet has to provide the charge r equired to turn off the lower mosfets body diode. this charge is conducted through the upper mosfet across vin, the power dissipated as a result, p umos,3 can be approxima ted as shown in equation 19. lastly, the conduction loss part of the upper mosfets power dissipation, p umos,4, can be calculated using equation 20. in this case, of course, r ds(on) is the on-resistance of the upper mosfet. the total power dissipated by the upper mosfet at full load can be approximated as the su mmation of these results. since the power equations depend on mosfet parameters, choosing the correct mosfets c an be an iterative process that involves repetitively solving the loss equations for different mosfets and differen t switching frequencies until converging upon the best solution. output filter design the output inductors and the outp ut capacitor bank together form a low-pass filter responsib le for smoothing the square wave voltage at the phase nod es. additionally, the output capacitors must also provide the energy required by a fast transient load during the short interval of time required by th e controller and power train to respond. because it has a low bandwidth compared to the swi tching frequency, the output filter limits the syst em transient response leaving t he output capacitor bank to supply the load current or sink the inductor currents, all while the curren t in the output inductors increases or decreases to meet the load demand. in high-speed converters, the output capacitor bank is amongst the costlier (and often the physically largest) parts of the circuit. output filter design begins with consideration of the critical load paramet ers: maximum s ize of the load step, ? i, the load-current slew ra te, di/dt, and the maximum allowable output voltage devia tion under trans ient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). p lmos1 r ds on ?? i out 2 ------------- ?? ?? ?? 2 1d C ?? i l p-p , 2 1d C ?? 12 ---------------------------------- + = (eq. 15) p lmos 2 v don ?? f s i out 2 ------------- i p-p 2 ---------- - + ?? ?? ?? t d1 i out 2 ------------- i p-p 2 ---------- - C ?? ?? ?? t d2 + = (eq. 16) p umos 1 , v in i out n ------------- i l p-p , 2 --------------- + ?? ?? ?? t 1 2 ---- ?? ?? ?? f s ? (eq. 17) p umos 2 , v in i out n ------------- i l p-p , 2 --------------- C ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ? (eq. 18) p umos 3 , v in q rr f s = (eq. 19) p umos 4 , r ds on ?? d i out n ------------- ?? ?? ?? 2 i p-p 2 12 ---------- - + ?? = (eq. 20)
ISL8101 fn9223 rev 1.00 page 16 of 20 july 28, 2008 at the beginning of the load trans ient, the outpu t capacitors supply all of the tr ansient current. the output voltage will initially deviate by an amoun t approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output- voltage deviation is less than the allowable maximum. neglecting the contri bution of inductor cu rrent and regulator response, the output voltage ini tially deviates according to equation 21. the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to suppor t the output voltage as the current increas es. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors is also responsible for the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current, a voltage develops across the bulk-capacitor esr equal to i p-p . thus, once the output capacitors are selected and a maximum allowable ripple voltage, v p-p(max) , is determined from an analysis of the available outpu t voltage budget. equation 22 can be used to dete rmine a lower limi t on the output inductance. since the capacitors are suppl ying a decreasing portion of the load current while the r egulator recovers from the transient, the capacitor volt age becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. while equation 23 addresses the leading edge, equation 24 gives the upper limit on l for cases where the trailing edge of the current transient cause s a greater out put voltage deviation than the leading edge. normally, the trailing edge dictate s the selection of l, since duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l s hould be selected based on the lower of the two re sults. in all equations in this paragraph, l is the per-channel inductance and c is the total output bulk capacitance. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions from one devic e to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, r adiate noise into the circuit and lead to device overvoltage stress. careful component layout and printed circuit de sign minimizes the voltage spikes in the converter. consider, as an example, the turn-off transition of the upper pwm mos fet. prior to turn-off, the upper mosfet was carrying channel current. during the turnoff, current stops flowing in the upper mo sfet and is picked up by the lower mos fet. any inductance in the switched current pat h generates a large voltage spike during the switching interval. caref ul component selection, tight layout of the critical compon ents, and short, wide circuit traces minimize the magni tude of voltage spikes. there are two sets of criti cal components in a dc/dc converter using a ISL8101 controller. the power components are the most critical because they switch large amounts of energy. next are sm all signal components that connect to sensitive nodes o r supply critical bypassing current and signal coupling. note that as the ISL8101 does not allow external adjustment of the channel-to-channel cu rrent balancing (current information is multiplexed ac ross a single r isen resistor), it is important to have a symmetrical layout, preferably with the controller equidistantly located from the two power trains it controls. equally important are t he gate drive lines (ugate, lgate, phase): since they drive the power train mosfets using short, high current pulses , it is important to size them accordingly and reduce their ov erall impedance. equidistant placement of the controller to the two power trains also helps keeping these traces equa lly long (equal impedances, resulting in similar driving of both sets of mosfets). the power components should be placed first. locate the input capacitors clos e to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. loca te the output inductors and output capacitors between t he mosfets and the load. locate the high-frequency decou pling capacitors (ceramic) as close as practicable to the decoupling target, making use of the shortest connection path s to any internal planes, such as vias to gnd immediately next, or even onto the capacitor solder pad. the critical small components include the bypa ss capacitors for vcc and pvcc. locate the bypass capacitors, c bp , ? v esl ?? di dt ---- - esr ??? i + ? (eq. 21) lesr v in 2v out ? C ?? v out ? f s v in v p-p max ?? ?? --------------------------------------------------------------- - - ? ? (eq. 22) l 4cv out ?? ? i ?? 2 -------------------------------- ? v max ? i esr ? C ?? ? ? (eq. 23) l 2.5 c ? ? i ?? 2 ---------------- - ? v max ? i esr ? C ?? v in v o C ?? ?? ? (eq. 24)
ISL8101 fn9223 rev 1.00 page 17 of 20 july 28, 2008 close to the device. it is espec ially important to locate the components associated with the feedback circuit close to their respective controller pi ns, since they belong to a high- impedance circuit loop, sensit ive to emi pick-up. it is important to place the r isen resistor close to the respective terminal of the ISL8101. a multi-layer printed circuit board is recommended. figure 10 shows the connections of the critical components for one output channel of the converte r. note that capacitors c xxin and c xxout could each represent numerous physical capacitors. dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a powe r plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the phase terminal to inductor l out short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signa l wiring. the wiring traces from the ic to the mosfets gates and sources should be sized to c arry at least one ampere of current (0.02 to 0.05). via connection to ground plane island on power plane layer island on circuit plane layer key locate close to ic figure 10. printed circuit board power planes and islands locate near load; (minimize connection path) ISL8101 +12v in q 1 q 2 q 3 q 4 vid4 vid3 vid2 vid1 vid0 comp fb gnd v cc boot1 boot2 ugate1 ugate2 isen lgate1 lgate2 l in l out1 (c hfin1 ) c bin1 (c hfin2 ) c bin2 c boot1 c boot2 l out2 (c hfout ) c bout r isen r 2 r 1 c 1 c 2 (c f1 ) phase1 phase2 v out pgnd p vcc (c f2 ) +5v in dacsel/vid12 vrm10 ssend enll r ofs ofs r ofs r 2 heavy trace on circuit plane layer locate near switching transistors; (minimize connection path) (minimize connection path)
ISL8101 fn9223 rev 1.00 page 18 of 20 july 28, 2008 component selection guidelines output capacitor selection the output capacitor is select ed to meet bot h the dynamic load requirements and the vo ltage ripple requirements. the load transient a microprocesso r impresses is characterized by high slew rate (di/dt) cu rrent demands. in general, multiple high quality capacitors of different size and dielectr ic are paralleled to meet the design constraints. should the load be characterized by high slew rates, attention should be particularly paid to t he selection and placement of high-frequency decoupling capacitors (mlccs, typically multi-layer ceramic capacitors ). high frequency capacitors supply the initially transi ent current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are genera lly determined by the esr (effective series resistance) and capacitance requirements. high frequency decoupling capaci tors should be placed as close to the power pins of the load, or for that reason, to any decoupling target they are mean t for, as physica lly possible. attention should be paid as no t to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. con sult with the manufacturer of the load on specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitors esr d etermines the output ripple voltage and the initial voltage drop following a high slew-rate transients edge. in most cases , multiple capacitors of small case size perform better than a s ingle large case capacitor. bulk capacitor choices include aluminum electrolytic, os-con, tantalum and even ceramic di electrics. an aluminum electrolytic capacitors esr v alue is related to the case size with lower esr available in l arger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified para meter. consult the capacitor manufacturer and/or measure the capacitors impedance with frequency to help select a suitable component. output inductor selection one of the parameters limiting the converters response to a load transient is th e time required to change the inductor current. in a multiphase conver ter, small inductors reduce the response time wit h less impact to the total output ripple current (as compared to s ingle-phase converters). the output inductor of each power channel controls the ripple current. the control ic is stable for channel ripple current (peak-to-peak) up to twice the aver age current. a single channels ripple curren t is approxima ted by using equation 25. the current from multiple channels tend to cancel each other and reduce the total ripple curr ent. the total output ripple current can be determined using the curve in figure 11; it provides the total r ipple current as a fu nction of d uty cycle and number of active channels, normalized to the parameter k norm at zero duty cycle (see equation 26). where l is the channel inductor value. find the intersection of the active channel curve and duty cycle for your parti cular application. t he resulting ripple current multiplier from the y-a xis is then multiplied by the normalization factor, k norm , to determine the total output ripple current for the given application (see equation 27). i lp-p ? v in v out C f sw l ? ------------------------------- - v out v in --------------- - ? = (eq. 25) k norm v out lf sw ? -------------------- = (eq. 26) i total ? k norm k cm ? = (eq. 27) 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) figure 11. ripple current vs duty cycle current multiplier, k cm
fn9223 rev 1.00 page 19 of 20 july 28, 2008 ISL8101 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2006-2008. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. input capacitor selection the important parameters for the bulk input capacitors are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at l east 1.25x greater than the maximum input voltage. the input rms current required for a multiphase converter can be approximated with the aid of figure 12. as the input capacitors are resp onsible for sourcing the ac component of the input curre nt flowing in to the upper mosfets, their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets. figure 12 can be used to determine the input-capacitor rms current function of duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l,p-p ) to the maximum sustained load current, i o . figure 12 can al so be used as a reference demonstrating the dramatic reduction in input capacitor rms current in a 2- phase dc/dc converter, as compared to a single-phase regulator. use a mix of input bypass capacitors to control the input voltage ripple. use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the rms current. minimize the co nnection path inductance of the high frequency decoupling ceramic capacitors (from drain of upper mosfet to s ource of lower mosfet). for bulk capacitance, several el ectrolytic or high-capacity mlc capacitors may be needed. for surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the cap acitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. 0.3 0.1 0 0.2 input capacitor current (i rms / i o ) figure 12. normalized input rms current vs duty cycle for a 2-phase converter 00.2 0.5 0.1 0.3 0.4 duty cycle (v o /v in ) i l,p-p = 0 i l,p-p = 0.5 x i o i l,p-p = 0.75 x i o
ISL8101 fn9223 rev 1.00 page 20 of 20 july 28, 2008 package outline drawing l24.4x4b 24 lead quad flat no-lead plastic package rev 2, 10/06 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 34 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2 . 34 0 . 15 pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:

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